The present invention relates in general to protocol conversion and tagging in networking systems and more particularly to techniques for converting multiple protocol types in a network accelerator to accommodate high bandwidth demand in an Asynchronous Transfer Mode (ATM) networking system.
The need for faster communication among computers and other systems requires ever faster and more efficient networks. Today, networks typically use an amalgam of various software and hardware to implement a variety of network functions and standards. Network devices such as client computer systems, servers, hubs, routers, switches, network backbones, etc., are each complex devices that require digital processing in hardware and software to facilitate network communication. Some tasks performed in a network device include translation between different network standards such as Ethernet and ATM, reformatting data, traffic scheduling, routing data cells, packets messages, etc. Depending on the particular protocol being implemented, some tasks may be performed at different points in the network.
In conventional networking systems that implement ATM, data traffic is handled by a Virtual Channel, or Virtual Connection (VC). There are typically many VCs in each system and each VC has its own characteristics, such as packet type, packet size and protocols. For each VC, a descriptor which identifies the particular VC and its characteristics and requirements is stored in a memory. When a scheduler determines that a particular VC is ready for transmission, the VC descriptor is accessed and processed to determine the appropriate characteristics and requirements for cell transmission on the particular connection.
In a typical network system, many different packets formatted according to different protocols are transported across the many various networking system devices using many VCs. When a packet is received over the network by a networking device, it is desirable to store the packet in a buffer for further processing of the information in the packet. For example, it is desirable to read information in a packet header and to add information to a packet header. Depending on the protocol used, the packet header size will vary accordingly. Adding information to a packet header is generally a slow process, limited by the time it takes to rebuild the packet and store it in a new buffer. Such rebuilding is usually done by software resident on a host CPU and can take many clock cycles to complete. It is therefore desirable to provide a networking device with the capability of adding information to a packet header without rebuilding the packet. It is also desirable to provide a generic packet header for all protocol types to improve processing efficiency.
The present invention provides novel techniques for accommodating multiple protocol encapsulation formats in a networking system. In particular, the techniques of the present invention provide systems and methods for adding information to a packet header without rebuilding and storing the packet in a second buffer location so as to assist in converting multiple protocol types.
According to the invention, systems and methods for assisting multiple protocol conversion in a network accelerator are provided. According to the invention, a network device includes a transmit processing engine, a receive processing engine and one or more memories, each memory including one or more buffers for storing packets. When packets are received, the receive engine is able to add a 4, 8, 12 or 16-byte tag to the front of each packet on a per-VC basis and store the packets buffers. Additionally, the receive engine is able to add an offset to the starting address of each packet in the buffer to which it is stored relative to the beginning of that buffer. When a packet is to be transmitted, the transmit engine is able to transmit the packet from an address that is offset from the starting address of the packet buffer by one or more bytes. Additionally, the transmit engine is able to add one of several predefined packet headers on a per-packet basis. In one embodiment, all components of the network device are implemented on a single semiconductor chip.
According to an aspect of the invention, a networking system device coupled to one or more networks is provided. The device typically comprises a memory including one or more buffers, each buffer for storing a packet, and a receive processing engine coupled to the memory. When a packet for a first one of a plurality of virtual channels (VCs) is received, the receive engine adds a per-VC tag to the beginning of the packet, wherein the tag is associated with the first VC, and wherein the receive engine stores the packet to a first one of the buffers.
According to another aspect of the invention, a networking system device coupled to one or more networks is provided. The device typically comprises a memory including one or more buffers, wherein a first packet for a first one of a plurality of VCs is stored in a first one of the buffers, and wherein the first packet is stored in the first buffer. The device also typically includes a transmit processing engine coupled to the memory, wherein when the first packet is ready to be transmitted, the transmit engine starts transmission of the first packet beginning at an offset address relative to the beginning of the first buffer.
According to yet another embodiment of the present invention, a networking system device coupled to one or more networks is provided. The device typically comprises a memory including one or more buffers, each buffer for storing a packet, and a receive processing engine coupled to the memory. When a first packet for a first one of a plurality of VCs is received, the receive engine adds a per-VC tag to the beginning of the packet, the tag being associated with the first VC, and wherein the receive engine stores the packet to a first one of the buffers. The device also typically includes a transmit processing engine coupled to the memory, wherein when the first packet is ready to be transmitted, the transmit engine starts transmission of the first packet beginning at a first offset address relative to the beginning of the first buffer.
According to an additional aspect of the invention, a method of processing a packet for transmission in a networking system device is provided, wherein the device is coupled to one or more networks, the device including a memory having one or more buffers, wherein the memory is coupled to a transmit processing engine and a receive processing engine. The method typically comprises the steps of receiving the packet on a first one of a plurality of virtual channels (VCs) by the receive engine, adding a tag to the beginning of the packet, the tag associated with the first VC, and storing the packet to a first one of the buffers. The method also typically includes the step of, when the first packet is ready to be transmitted, starting transmission of the packet beginning at a first offset address relative to the beginning of the first buffer by the transmit engine.
Reference to the remaining portions of the specification, including the drawings and claims, will realize other features and advantages of the present invention. Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with respect to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements.